1. Field of the Invention
The present invention relates to Analog-to-Digital conversion of electrical signals and, more particularly, to apparatus and methods of rejecting the power line-frequency noise within the process of conversion.
2. Description of Related Art
Digital processing and transmission of electrical signals has become commonplace in many industrial and consumer applications. Applying digital methods to analog information requires an analog-to-digital (A/D) conversion, but the needed linearity, resolution, and speed of such a conversion depends on the application. For example, many industrial control applications require A/D conversion with good linearity and high resolution (12-24 bits) but the necessary conversion or data throughput rate is relatively slow (20 Hz or less); whereas, video applications demand high speed (20 MHz or more) but tolerate lower resolution (8 bits) and poorer linearity. Intermediate speed applications (12 bits, 1-5 MHz) appear in document scanners and facsimile machines.
Industrial control and test and measurement applications typically monitor parameters, such as pressure and temperature, that essentially are slow time varying dc voltage levels. The measurements are performed by using a transducer to sense the physical parameter and generate an analog electrical signal that the A/D converter transforms into a digital representation for processing in a computer or microprocessor.
There are three types of A/D converters typically used in these industrial control applications: (1) integrating converters with 8 to 16 bit resolution which are inexpensive but slow (usually less than 50 conversions per second); (2) successive approximation register (SAR) converters with 12 to 16 bit resolution which are much faster, however, these converters with their required sample-and-hold circuit are very expensive; and (3) sigma delta converters with 16 to 22 bit resolution which are inexpensive but slow based on existing architectures.
Sigma delta analog-to-digital converters consist of two major elements, a modulator that oversamples and digitizes an input analog signal, and a digital filter that removes unwanted noise. In low frequency industrial control and test and measurement applications, the filtering operation must remove internally generated quantization and other noise and externally generated interference noise.
The most common form of interference noise for industrial control and test and measurement instruments is AC power-line noise with the frequencies of 50 of 60 Hz and their harmonics. The mechanism of A C line noise intereference is inductive and/or capacitive coupling of power-line-frequency to sensor leads and to the imput of measurement circuitry. The coupled signal forms a normal mode noise superimposed on the signal of interest to be measured. This noise must be removed from the signal of interest or be rejected during the analog to digital conversion for an accurate result.
The usual solution to such a noise problem is the inclusion of a lowpass filter at the input of an A/D converter. FIG. 1 shows a block diagram of such a solution. In order to achieve an acceptable accuracy in the filter's passband and high rejection in the filter's stopband, a very high order filter should be used. This is often complicated and expensive filter. In addition, the filter has a long setting time to be added to the A/D conversion time.
Another technique for improving the AC line-frequency rejection is the use of the inherent characteristics of the A/D converter. This in particular, is applicable to sigma delta and integrating A/D converters. These A/D converters have the following inherent properties in common:
1. The frequency response of their input-output transfer function have multiple zeros which provide notch filter characteristics and allows selected frequencies to be highly rejected.
2. The frequency response of their input-output transfer function, and more particularly the location of the zeroes, is a function of the A/D converter clock frequency.
From the above properties, the AC line-frequency will be rejected if it lies at one of the zeroes of the A/D converter transfer function. In all the implementations this can be accomplished by selection of the clock frequency to be an appropriate fixed integer multiple of the AC line-frequency. A crystal oscillator is often used for clock generation to provide a stable clock frequency. FIG. 2 shows a block diagram of such a solution eliminating the need of filter in FIG. 1.
As a first example, sigma-delta converters often use a digital comb filter for the digital filtering of the sigma-delta modulator output due to its acceptable performance with a simple implementation. A sigma-delta modulator of order L requires a comb filter with the order of N=L+1 to provide adequate quantization noise attenuation. An Nth order comb filter has an amplitude frequency response of [sin(.pi.f/F)/(.pi.f/F)].sup.N where f is the input frequency and F is the first notch frequency of the filter. FIG. 3 shows a typical amplitude frequency response of a comb filter for N=3 and F=10 Hz for the input frequency range of f=0 to 100 Hz. It can be seen that by designing the comb filter with its first notch frequency as an integral fraction of the AC line-frequency, the rejection of AC line noise will be very high.
As a second example, the cross-referenced patent application of Sramek provides a sigma-delta converter architecture which uses a high cutoff lowpass and decimation digital filter (with a passband much beyond the 50 or 60 Hz frequency of the AC line) to digitize the signal at an output rate which is a multiple of the AC line frequency. Then a simple running average of its last M output samples is computed to average out and reject the AC line-frequency. The normal mode rejection ratio of the running average block versus frequency has the form of EQU Msin(P)/.SIGMA.[sin(P+(2.pi.mf)/F)]with summation over m=0,1,...,M-1
where M is the number of samples to be averaged, F is the input data sampling rate for the running average block (which is the output rate of the high cutoff and decimination digital filter), P is the phase shift of the input sine wave to the M.sup.th previous sample and f is the frequency of the input sine wave. FIG. 4 shows a typical normal mode rejection ratio (NMRR) of this architecture for M=4, F=240 Hz and P=.pi./4 for the input frequency range of f=0 to 240 Hz. It can be seen that, by proper selection of M and F the AC line frequency 60 Hz can be highly rejected during the running average computation.
As a third example, integrating converters use a fixed time interval for integration of the input signal. The integrator output voltage at the end of the fixed time interval is proportional to the input and will be converted to a digital representation in the following phases of the conversion cycle. The normal mode rejection of the integrating converter is defined as a ratio of the integrator output for a DC input (frequency of zero) to the integrator output for a sinusoidal input. The normal mode rejection ratio of an integrating converter has the form of (2.pi.fT)/(cosP-cos(2.pi.fT+P)) where f is the input signal frequency, T is the integrating time interval and P is the phase shift of the input signal to the start of the integration phase. FIG. 5 shows a typical NMRR of an integrating converter for T=1/60 of a second, P=.pi./2 (worst case) and input frequency range of f=0 to 180 Hz. It can be seen that by proper selection of the T the AC line frequency (60 Hz) can be highly rejected during the integration cycle of the converter.
The architecture shown in FIG. 2 is widely used in conjunction with the mentioned A/D converters for precision measurement of DC and slow varying signals. However, this architecture has a problem of not accounting for the frequency variations of the AC power line. Unfortunately, deviation of the line frequency of .+-.2 Hz (up to .+-.3 Hz in the worst case) are normal. This variation drastically reduces the NMRR of the AC line-frequency while the crystal clock frequency is stable. FIG. 6 shows the same frequency response as of FIG. 3 for .+-.2 Hz variation about 60 Hz. It can be seen that due to the narrowness of the notch characteristics the AC line-frequency rejection will drop to about 90 dB from better that 180 dB for frequencies of 58 and 62 Hz. FIG. 7 and 8 show the same NMRR as of FIGS. 4 and 5 respectively for .+-.2 Hz variation about the 60 Hz. It can also be seen in both cases that rejection of the AC line frequency will drop significantly for frequencies deviated from 60 Hz.